1. Technical Field
Various embodiments generally relate to a stack package, and more particularly, to a stack package and semiconductor integrated circuit device including a variable voltage.
2. Related Art
In order to increase the degree of integration in a memory chip, a two-dimensional (2D) structure including a plurality of the memory chips may be arranged on a single plane. The memory chip may be converted into a three-dimensional (3D) structure. In a 3D structure the memory chips may be stacked. Memory chips having high degrees of integration and high capacity may be required. To satisfy this requirement the 3D structure of the memory chips may be used to increase the capacity and reduce a size of a semiconductor chip. Thus, improving the integration degree of the memory chip.
The 3D structure may implement a through silicon via (TSV) technique. The TSV technique may be used for improving low transmission speeds. Low transmission speeds may be caused by a distance of a controller on a module, by variables on a package, and a weak data bandwidth.
In the TSV technique, a hole may be formed through the memory chips. An electrode may be formed in the hole. Communication between the memory chips may be performed through the electrodes.